In this lab, you are asked to implement and simulate your simplified circuit from Lab 1 in VHDL using or similar. This assignment is to be completed in the groups from Lab 2 or you may great a new group of two. Each group is expected to complete the lab independently. Submit the following to me, with descriptions of each section:

Edit code – EDA Playground

Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

– Schematic, labeled with the signals, ports and entities to be used. Labels must match your implementation.

– VHDL design and testbench files, using structural programming.

– Simulation output and a comparison with expected output.


This is function that i want u to coding

F=Y+X’Y’ is not that hard

I need u to do it like the example the file

i need the same form please

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